Designing the dispatch stage of a superscalar microprocessor

The design of a superscalar microprocessor poses several challenging problems concerning both its architectural conception and VLSI implementation. This paper discusses the main aspects in the design of the dispatch stage of the Superflux superscalar processor. First, it presents a methodology direc...

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Bibliographic Details
Main Authors: Alcantara, J.M.S., Alves, V.C., Filho, E.M.C.
Format: Conference Proceeding
Language:English
Subjects:
Cache memory
Clocks
Decoding
Dynamic scheduling
Electrical capacitance tomography
Microprocessors
Pipeline processing
Processor scheduling
Read only memory
Very large scale integration
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Summary:The design of a superscalar microprocessor poses several challenging problems concerning both its architectural conception and VLSI implementation. This paper discusses the main aspects in the design of the dispatch stage of the Superflux superscalar processor. First, it presents a methodology directed to the cooperative development of a large VLSI project. Then, it shows how the methodology is applied to the design of Superflux's dispatch stage. The approach described can be immediately applied or easily adapted/extended to other large VLSI designs. Although superscalar processors are now present in systems from microcomputers to large multiprocessors, few papers have been published about the practical design of these devices. This paper contributes with an introductory view to this task.
DOI:10.1109/SBCCI.1998.715429