A new compact high-efficiency mmWave power amplifier in 65 nm CMOS process

This paper presents a new design technique for high-efficiency CMOS mmWave power amplifier (PA). The proposed PA adopts NMOS capacitors connected at the gates of the transistors of the last amplifying stage to compensate gate capacitance variation over large signal swing, improving the linearity and...

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Bibliographic Details
Main Authors: Tianzuo Xi, Huang, Sherry, Guo, Shita, Ping Gui, Jing Zhang, Wooyeol Choi, Daquan Huang, Kenneth, K. O., Fan, Yanli
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
capacitance linearization
Capacitors
CMOS integrated circuits
CMOS technology
high efficiency
Logic gates
mmWave
MOS devices
NMOS capacitors
Power amplifier (PA)
Tracking loops
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Description
Summary:This paper presents a new design technique for high-efficiency CMOS mmWave power amplifier (PA). The proposed PA adopts NMOS capacitors connected at the gates of the transistors of the last amplifying stage to compensate gate capacitance variation over large signal swing, improving the linearity and the power efficiency. Implemented in 65 nm CMOS process, the presented PA consists of two differential stages, uses baluns, transformers and inductors to realize the input, output, and inter-stage power matching, and achieves a peak PAE of 24.2%, a 6 dB back-off PAE of 10.5% from 3 dB gain compression, a maximum gain of 17 dB, and a 3-dB bandwidth from 68 to 78 GHz.
ISSN:0149-645X
2576-7216
DOI:10.1109/MWSYM.2015.7167051