RENO: a high-efficient reconfigurable neuromorphic computing accelerator design

• Main Authors: Liu, Xiaoxiao, Mao, Mengjie, Liu, Beiye, Li, Hai, Chen, Yiran, Li, Boxun, Wang, Yu, Jiang, Hao, Barnell, Mark, Wu, Qing, Yang, Jianhua
• Format: Conference Proceeding
• Language: English
• Subjects: Accuracy; Active appearance model; Arrays; Artificial neural networks; Hardware > Electronic design automation > Physical design (EDA); Hardware > Hardware validation; Hardware > Very large scale integration design > Application-specific VLSI designs; Memristors; Routing; Training
• ISSN: 0738-100X
• DOI: 10.1145/2744769.2744900

Neuromorphic computing is recently gaining significant attention as a promising candidate to conquer the well-known von Neumann bottleneck. In this work, we propose RENO -- a efficient reconfigurable neuromorphic computing accelerator. RENO leverages the extremely efficient mixed-signal computation capability of memristor-based crossbar (MBC) arrays to speedup the executions of artificial neural networks (ANNs). The hierarchically arranged MBC arrays can be configured to a variety of ANN topologies through a mixed-signal interconnection network (M-Net). Simulation results on seven ANN applications show that compared to the baseline general-purpose processor, RENO can achieve on average 178.4x (27.06x) performance speedup and 184.2x (25.23x) energy savings in high-efficient multilayer perception (high-accurate auto-associative memory) implementation. Moreover, in the comparison to a pure digital neural processing unit (D-NPU) and a design with MBC arrays co-operating through a digital interconnection network, RENO still achieves the fastest execution time and the lowest energy consumption with similar computation accuracy.