Area-efficient pipelining for FPGA-targeted high-level synthesis

Traditional techniques for pipeline scheduling in high-level synthesis for FPGAs assume an additive delay model where each operation incurs a pre-characterized delay. While a good approximation for some operation types, this fails to consider technology mapping, where a group of logic operations can...

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Bibliographic Details
Main Authors: Zhao, Ritchie, Tan, Mingxing, Dai, Steve, Zhang, Zhiru
Format: Conference Proceeding
Language:English
Subjects:
Benchmark testing
Delays
Hardware > Electronic design automation > High-level and register-transfer level synthesis
Hardware > Hardware validation
Hardware > Very large scale integration design > Application-specific VLSI designs
Kernel
Pipeline processing
Registers
Schedules
Table lookup
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Description
Summary:Traditional techniques for pipeline scheduling in high-level synthesis for FPGAs assume an additive delay model where each operation incurs a pre-characterized delay. While a good approximation for some operation types, this fails to consider technology mapping, where a group of logic operations can be mapped to a single look-up table (LUT) and together incur one LUT worth of delay. We propose an exact formulation of the throughput-constrained, mapping-aware pipeline scheduling problem for FPGA-targeted high-level synthesis with area minimization being a primary objective. By taking this cross-layered approach, our technique is able to mitigate the pessimism inherent in static delay estimates and reduce the usage of LUTs and pipeline registers. Experimental results using our method demonstrate improved resource utilization for a number of logic-intensive, real-life benchmarks compared to a state-of-the-art commercial HLS tool for Xilinx FPGAs.
ISSN:0738-100X
DOI:10.1145/2744769.2744801