Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access sta...

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Main Authors: Meinerzhagen, Pascal, Bonetti, Andrea, Karakonstantis, Georgios, Roth, Christoph, Giirkaynak, Frank, Burg, Andreas
Format: Conference Proceeding
Language:English
Subjects:
Decoding
Memory management
Microprocessors
Parity check codes
Random access memory
Tin
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creator Meinerzhagen, Pascal
Bonetti, Andrea
Karakonstantis, Georgios
Roth, Christoph
Giirkaynak, Frank
Burg, Andreas
description The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).
doi_str_mv 10.1109/ISCAS.2015.7168911
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subjects Decoding
Memory management
Microprocessors
Parity check codes
Random access memory
Tin
title Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder
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