Enhanced level shifter for multi-voltage operation

A novel level-up shifter with dual supply voltage is proposed. The proposed design significantly reduces the short circuit current in conventional cross-coupled topology, improving the transient power consumption. Compared with the bootstrapping technique, the proposed circuit consumes significantly...

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Bibliographic Details
Main Authors: Weicheng Liu, Salman, Emre, Sitik, Can, Taskin, Baris
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Delays
MOSFET
Short-circuit currents
Simulation
Topology
Transient analysis
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Description
Summary:A novel level-up shifter with dual supply voltage is proposed. The proposed design significantly reduces the short circuit current in conventional cross-coupled topology, improving the transient power consumption. Compared with the bootstrapping technique, the proposed circuit consumes significantly less area, making it more practical for ICs with a large number of supply voltages. The minimum power-delay product (PDP) for each level shifter is analyzed and compared. Worst-case corner analysis is performed for transient power, delay, and leakage power. The dependence of power and delay on input supply voltage level is also investigated for each topology. Simulation results demonstrate 43% and 36% reduction in, respectively, transient power and leakage power as compared to cross-coupled level shifter, while consuming 9.5% and 79.5% less physical area than, respectively, cross-coupled and bootstrapping techniques.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2015.7168915