System-Level Modeling for Transient Electrostatic Discharge Simulation

This paper introduces an improved electrostatic discharge (ESD) system-level transient simulation modeling method and discusses its validation using IEC 61000-4-2 ESD pulses on a real-world product. The system model is composed of high current and broadband (up to 3 GHz) models of R, L, C, ferrite b...

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Bibliographic Details
Published in:IEEE transactions on electromagnetic compatibility 2015-12, Vol.57 (6), p.1298-1308
Main Authors: Tianqi Li, Pilla, Viswa, Zhen Li, Maeshima, Junji, Shumiya, Hideki, Araki, Kenji, Pommerenke, David J.
Format: Article
Language:English
Subjects:
Capacitors
Common mode
Computer simulation
Diodes
Electromagnetic compatibility
electromagnetic compatibility (EMC)
electrostatic discharge (ESD)
Electrostatic discharges
Hidden Markov models
human machine model (HMM)
IEC 61000-4-2
Integrated circuit modeling
Integrated circuits
Junctions
Materials information
Melting
Semiconductor device modeling
Semiconductor diodes
system efficient ESD design (SEED)
transmission line pulser (TLP)
Waveforms
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Summary:This paper introduces an improved electrostatic discharge (ESD) system-level transient simulation modeling method and discusses its validation using IEC 61000-4-2 ESD pulses on a real-world product. The system model is composed of high current and broadband (up to 3 GHz) models of R, L, C, ferrite beads, diodes, and integrated circuit IO pins. A complex return path model is the key to correctly model the system's response to the IEC excitation. The model includes energy-limited time-dependent IC damage models. A power-time integral method is introduced to accurately determine if a junction would experience thermal runaway under an arbitrary injection waveform. The proposed method does not require knowledge of the junction's microscopic geometry, material information, defect location, or melting temperature.
ISSN:0018-9375
1558-187X
DOI:10.1109/TEMC.2015.2443844