A low power transregional MOSFET model for complete power-delay analysis of CMOS gigascale integration (GSI)

• Main Authors: Austin, B.L., Bowman, K.A., Xinghai Tang, Meindl, J.D.
• Format: Conference Proceeding
• Language: English
• Subjects: Circuit synthesis; Contracts; Degradation; Integrated circuit modeling; MOSFET circuits; Performance analysis; Power MOSFET; Semiconductor device modeling; Transmission line measurements; Voltage
• ISSN: 1063-0988; 2164-1773
• DOI: 10.1109/ASIC.1998.722816

A new compact transregional model for conventional surface channel inversion MOSFETs with continuous and smooth transitions at regional boundaries is introduced. The model, verified against MEDICI and HSPICE, describes all regions of operation, namely, subthreshold, linear, and saturation while including the effects of 1) carrier velocity saturation, 2) vertical and lateral high field mobility degradation, and 3) threshold voltage roll-off, all prominent characteristics of sub-micron devices. The key contribution of this model is the physical insight into the on/off current trade-off that ensues with voltage scaling and will be vital to future low power design. Utilizing the model for a complete power-delay analysis of CMOS circuit designs, analytical expressions are derived for: 1) propagation delay, 2) short circuit power (P/sub SC/), and 3) static power (P/sub Static/). Results from the total power (P/sub Total/) consumption analysis indicate that P/sub SC/ and P/sub Static/ may constitute over 1/3 of P/sub Total/ in future low power/high performance CMOS GSI.