Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment

• Published in: IEEE transactions on device and materials reliability 2015-12, Vol.15 (4), p.626-628
• Main Authors: Gimenez, Salvador Pinillos, Galembeck, Egon Henrique Salerno, Renaux, Christian, Flandre, Denis
• Format: Magazinearticle
• Language: English
• Subjects: CMOS integrated circuits; CMOS technology; Diamonds; high temperature environment; Layout; LCE effect and PAMDLE effect; leakage drain current; Logic gates; MOSFET; OCTO layout style; Semiconductors; Temperature effects
• ISSN: 1530-4388; 1558-2574
• DOI: 10.1109/TDMR.2015.2474739

The impact of high-temperature effects is experimentally investigated in the octagonal layout style for planar silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs), named OCTO SOI MOSFETs (OSMs), in relation to the hexagonal [diamond SOI MOSFETs (DSMs)] and the standard (rectangular conventional SOI MOSFETs) ones regarding the same bias conditions. The devices were manufactured with a 1-μm fully depleted SOI complementary MOS (CMOS) technology. The main experimental findings demonstrate that OSM is capable of keeping active the longitudinal corner effect and the PArallel connection of MOSFET with Different channel Lengths Effect (PAMDLE) in its structure at high-temperature conditions, and consequently, it maintains its remarkably better electrical performance in comparison with the standard SOI MOSFET, mainly its capacity to reduce the leakage drain current, without causing any extra burden to the current planar SOI CMOS technology in relation to DSMs.