7.4μW Ultra-high slew-rate pseudo single-stage amplifier driving 0.1-to-15nF capacitive load with >69° phase margin

To achieve ultra-high slew-rate with stable operation under wide capacitive load range, pseudo single-stage amplifier is proposed in this paper. The proposed amplifier achieves widest capacitive load drivability (x150). Also, this work achieves at least 151 times larger FOM for slew-rate compared to...

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Main Authors: Sung-Wan Hong, Gyu-Hyeong Cho
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
CMOS process
Feedback loop
Logic gates
Mirrors
Resistance
Transient analysis
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creator Sung-Wan Hong
Gyu-Hyeong Cho
description To achieve ultra-high slew-rate with stable operation under wide capacitive load range, pseudo single-stage amplifier is proposed in this paper. The proposed amplifier achieves widest capacitive load drivability (x150). Also, this work achieves at least 151 times larger FOM for slew-rate compared to state-of-the-art works. This chip was fabricated using a 0.18 μm CMOS process with area of 0.0021 mm 2 .
doi_str_mv 10.1109/VLSIC.2015.7231297
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Capacitors
CMOS process
Feedback loop
Logic gates
Mirrors
Resistance
Transient analysis
title 7.4μW Ultra-high slew-rate pseudo single-stage amplifier driving 0.1-to-15nF capacitive load with >69° phase margin
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