Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing

In this paper, we present an optimized design for the quantum ternary adder/subtract or circuit. We propose the design of quantum Ternary Peres Gate (TPG). The design of our proposed quantum ternary adder/subtract or circuit consists of two parts: a) Firstly, it has the design of a quantum ternary f...

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Bibliographic Details
Main Authors: Lisa, Nusrat Jahan, Md Hasan Babu, Hafiz
Format: Conference Proceeding
Language:English
Subjects:
Adder/Subtractor Circuit
Adders
Algorithm design and analysis
Complexity theory
Computers
DH-HEMTs
Garbage Outputs
Logic gates
Quantum computing
Quantum Logic
Ternary Peres Gate
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Summary:In this paper, we present an optimized design for the quantum ternary adder/subtract or circuit. We propose the design of quantum Ternary Peres Gate (TPG). The design of our proposed quantum ternary adder/subtract or circuit consists of two parts: a) Firstly, it has the design of a quantum ternary full-adder circuit using the proposed TPG gates, and b) Secondly, it designs the proposed adder/subtract or circuit by using the constructed full-adder in a) and M-S gates. We also propose a heuristic to design a compact ternary adder/subtract or circuit. Our circuits perform much better than the existing ones.
ISSN:0195-623X
2378-2226
DOI:10.1109/ISMVL.2015.23