Low Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read- VDDmin, and slow read access time (T AC ) caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2015-11, Vol.50 (11), p.2786-2795
Main Authors: Meng-Fan Chang, Jui-Jen Wu, Tun-Fei Chien, Yen-Chen Liu, Ting-Chin Yang, Wen-Chao Shen, Ya-Chin King, Chrong Jung Lin, Ku-Feng Lin, Yu-Der Chih, Chang, Jonathan
Format: Article
Language:English
Subjects:
Arrays
Nonvolatile memory
ReRAM
Resistance
RRAM
sense amplifier
Sensors
Switches
Switching circuits
Transistors
voltage-mode sense amplifier
write driver
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Summary:The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read- VDDmin, and slow read access time (T AC ) caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current (I DC -SET) resulting from the wide distribution of write (SET)-times (T SET ). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately 1.8+x greater sensing margin for lower VDD min and a 1.7+x faster read speed across a wide VDD range, compared with conventional VSAs. A 4T self-boost-write-termination (SBWT) scheme is proposed to cut off the I DC -SET of devices with a rapid T SET. The SBWT scheme reduces 99+% of the I DC -SET with an area penalty below 0.5%. A fabricated 512 row 28 nm 1 Mb ReRAM macro achieved T AC = 404 ns when VDD=0.27 V and confirmed the I DC -SET cutoff by the SBWT.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2015.2472601