Boundary element method macromodels for 2-D hierarchical capacitance extraction

A 2-D hierarchical field solution method was recently introduced for capacitance extraction for VLSI interconnect modeling. In this paper, we present several extensions to the method including a Boundary Element Method (BEM) formulation for creating macromodels, which provides a better trade-off bet...

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Bibliographic Details
Main Authors: Dengi, E.A., Rohrer, R.A.
Format: Conference Proceeding
Language:English
Subjects:
Boundary element methods
Capacitance
Conductors
Finite difference methods
Integrated circuit interconnections
Integrated circuit yield
Libraries
Permission
Runtime
Very large scale integration
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Summary:A 2-D hierarchical field solution method was recently introduced for capacitance extraction for VLSI interconnect modeling. In this paper, we present several extensions to the method including a Boundary Element Method (BEM) formulation for creating macromodels, which provides a better trade-off between accuracy and efficiency, as well as parameterized elements, which allow the analysis of gridless designs with reasonable accuracy and a small library size.
DOI:10.1109/DAC.1998.724470