Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2016-05, Vol.24 (5), p.1895-1908
• Main Authors: Yin, Shouyi, Yao, Xianqing, Liu, Dajiang, Liu, Leibo, Wei, Shaojun
• Format: Article
• Language: English
• Subjects: Arrays; Cascading style sheets; Coarse-grained reconfigurable architectures (CGRAs); Kernel; loop pipelining; memory-aware mapping; modulo scheduling; Registers; Routing; Topology
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2015.2474129

The coarse-grained reconfigurable architectures (CGRAs) are a promising class of architectures with the advantages of high performance and high power efficiency. The compute-intensive parts of an application (e.g., loops) are often mapped onto the CGRA for acceleration. Due to the extra overhead of memory access and the limited communication bandwidth between the processing element (PE) array and local memory, previous works trying to solve the routing problem are mainly confined in the internal resources of PE arrays (e.g., PEs and registers). Inevitably, routing with PEs or registers will consume a lot of computational resources and cause the increase of the initiation interval. To solve this problem, this paper makes two contributions: 1) establishing a precise formulation for the CGRA mapping problem while using shared local data memory as a routing resource and 2) extracting an effective approach for mapping loops to CGRAs. The experimental results on loops of the SPEC2006, Livermore, and MiBench show that our approach (called MEMMap) can improve the performance of the kernels on CGRA up to 1.62×, 1.58×, 1.28×, and 1.23× compared with the edge-centric modulo scheduling, EPIMap, REGIMap, and force-directed map, respectively, with an acceptable increase in compilation time.