A 10-bit 40-MS/s Time-Domain Two-Step ADC With Short Calibration Time

A 10-bit 40-MS/s time-domain two-step analog-to-digital converter (ADC) in a 0.18-μm CMOS process is presented. The proposed ADC is realized without any high-gain amplifiers and its calibration time requires only 622 clock cycles, which is over 10 times less than prior digitally calibrated ADCs. The...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2016-02, Vol.63 (2), p.126-130
Main Authors: Chen, Liang-Jen, Liu, Shen-Iuan
Format: Article
Language:English
Subjects:
Calibration
calibration time
Capacitors
Circuits
Clocks
CMOS
Delays
digital calibration
Distortion
Dynamic range
Engines
Noise levels
Noise measurement
Signal to noise ratio
Time-domain
Time-domain analysis
two-step ADC
voltage-to-time converter
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Summary:A 10-bit 40-MS/s time-domain two-step analog-to-digital converter (ADC) in a 0.18-μm CMOS process is presented. The proposed ADC is realized without any high-gain amplifiers and its calibration time requires only 622 clock cycles, which is over 10 times less than prior digitally calibrated ADCs. The measured spurious-free dynamic range (SFDR) and signal-to-noise-plus distortion ratio (SNDR) are 61.3 dB and 53.8 dB at 40 MS/s, respectively. The power and area are 6.1 mW and 0.75 mm 2 , respectively.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2015.2483360