A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer

This paper presents a wireline receiver design of CMOS I/O at 10-Gb/s data rate. A power efficient continuous-time linear equalizer (CTLE) and 1-tap lookahead decision feedback equalizer (DFE) are designed and implemented in a 45 nm CMOS technology. The DFE employs a sampler including a current inje...

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Bibliographic Details
Main Authors: Yongsuk Choi, Yong-Bin Kim
Format: Conference Proceeding
Language:English
Subjects:
Clocks
CMOS integrated circuits
Continuous-time linear equalizer
decision feedback equalizer
Decision feedback equalizers
high-speed I/O
Noise
receiver
Receivers
serial link
speculative
Timing
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Summary:This paper presents a wireline receiver design of CMOS I/O at 10-Gb/s data rate. A power efficient continuous-time linear equalizer (CTLE) and 1-tap lookahead decision feedback equalizer (DFE) are designed and implemented in a 45 nm CMOS technology. The DFE employs a sampler including a current injection section that makes no use of summer as a separated block. In addition, cascode structure increases kick-back noise immunity and reduces power consumption by 11%. The PLL used in the proposed receiver drives 5 GHz clock frequency with 12.62 ps pk-pk jitter. The core receiver circuit consumes 14.3 mW at a 1.1 V supply voltage when processing 10 Gb/s data rate with 15 dB of channel loss at Nyquist frequency.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2015.7282072