A 56-Gb/s Wireline Transceiver in 20nm CMOS

A feasibility of a 56-Gb/s CMOS transceiver is discussed. Simulations showed that the CMOS-inverter-based transmitter can generate 56-Gb/s signals with an inductive peaking. A receiver front- end suited for baud-rate clock recovery is demonstrated in 20-nm CMOS. Sharing the comparators for the data...

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Bibliographic Details
Main Authors: Shibasaki, Takayuki, Yanfei Chen, Yoshiyasu Doi, Takauchi, Hideki, Mori, Toshihiko, Koyanagi, Yoichi, Tamura, Hirotaka
Format: Conference Proceeding
Language:English
Subjects:
Clocks
CMOS integrated circuits
Decision feedback equalizers
Phase detection
Receivers
Transceivers
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Summary:A feasibility of a 56-Gb/s CMOS transceiver is discussed. Simulations showed that the CMOS-inverter-based transmitter can generate 56-Gb/s signals with an inductive peaking. A receiver front- end suited for baud-rate clock recovery is demonstrated in 20-nm CMOS. Sharing the comparators for the data decision and phase detection minimizes the number of comparators in the front-end and reduces the power consumption. The front-end has a continuous-time linear equalizer followed by a 1-tap speculative decision-feedback equalizer. The front- end operates at 56Gb/s with a bit error rate of less than 10 -12 with a 0.4UI margin in the bathtub curve. It occupies 0.27mm 2 and consumes 177mW of power from a 0.9-V supply.
ISSN:1550-8781
2374-8443
DOI:10.1109/CSICS.2015.7314471