Design and Demonstration of Power Delivery Networks With Effective Resonance Suppression in Double-Sided 3-D Glass Interposer Packages

• Published in: IEEE transactions on components, packaging, and manufacturing technology (2011) packaging, and manufacturing technology (2011), 2016-01, Vol.6 (1), p.87-99
• Main Authors: Kumar, Gokul, Sitaraman, Srikrishna, Jonghyun Cho, Sundaram, Venky, Joungho Kim, Tummala, Rao R.
• Format: Article
• Language: English
• Subjects: 3-D interposers; Arrays; Capacitors; Design engineering; Electric power; Electricity distribution; Electricity generation; Glass; glass interposers; Glass substrates; Impedance; Logic; logic memory bandwidth; Networks; Packages; power delivery; Silicon; Solid modeling; Stacking; Substrates; Three dimensional; through-package-vias; Through-silicon vias; TSVs
• ISSN: 2156-3950; 2156-3985
• DOI: 10.1109/TCPMT.2015.2478466

Ultrathin 3-D glass interposers with throughpackage vias at the same pitch as through-silicon vias (TSVs) have been proposed as a simpler and cheaper alternative to the direct 3-D stacking of logic and memory devices. Such 3-D interposers provide wide-I/O channels for high signal bandwidth (BW) between the logic device on one side of the interposer and memory stack on the other side, without the use of complex TSVs in the logic die. However, this configuration introduces power delivery design challenges due to resonance from: 1) the low-loss property of the glass substrate and 2) the parasitic inductance due to additional length from lateral power delivery path. This paper presents for the first time, the design and demonstration of power delivery networks (PDNs) in 30-μm thin, 3-D double-sided glass interposers, by suppressing the noise from mode resonances. The self-impedance of the 3-D glass interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board and chip-level models. The 3-D PDN was compared with that of the 2-D glass packages having fully populated ball grid array connections. The resonance mechanism for each configuration was studied in detail, and the corresponding PDN loop inductances were evaluated. High impedance peaks in addition to the 2-D PDN were observed at high frequencies (near 7.3 GHz) in the 3-D interposer structure due to the increased inductances from lateral power delivery. This paper proposes and evaluates three important resonance suppression techniques based on: 1) 3-D interposer die configuration; 2) the selection and placement of decoupling capacitors; and 3) 3-D interposer package power and ground stack-up. Two-metal and four-metal layer test vehicles were fabricated on 30and 100-μm thick panel-based glass substrates, respectively, to validate the modeling and analysis of the proposed approach. The PDN test structures were characterized up to 20 GHz for plane resonances and network impedances, with good model-to-hardware correlation. The results in this paper suggest that the ultrathin 3-D interposer PDN structure can be effectively designed to meet the target impedance guidelines for high-BW applications, providing a compelling alternative to 3-D-IC stacking with the TSVs.