Multiobjective optimization of VLSI interconnect parameters

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 1998-12, Vol.17 (12), p.1252-1261
• Main Authors: Anand, M.B., Shibata, H., Kakumu, M.
• Format: Article
• Language: English
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Dielectric materials; Electronics; Exact sciences and technology; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit synthesis; Integrated circuit technology; Integrated circuits; Large scale integration; Parasitic capacitance; Power system modeling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Very large scale integration; Wire
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.736565

The significant role played by interconnects in determining the speed and chip size of very-large-scale integrated circuits (VLSI) necessitates the development of new processes and tools for almost every device generation. Since such development usually requires lead times of several years, it has become essential to know, several years in advance, the various interconnect parameters for a particular generation. In this paper, a tool for optimizing interconnect parameters is presented. The formulation of an optimization problem that can be solved using standard algorithms is shown to be possible, and the optimization results obtained for future device generations are discussed. These results can be used to construct an interconnect technology roadmap. Last, shortcomings of and possible improvements to existing system-level critical path models are discussed.