Fixed-point error analysis and word length optimization of 8/spl times/8 IDCT architectures

Complete fixed-point error models that include the coefficient quantization are derived for two popular 8/spl times/8 two-dimensional (2-D) IDCT architectures; one is based on distributed arithmetic, and the other is the multiplier-adder chain. The error models are evaluated in the integer domain to...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems for video technology 1998-12, Vol.8 (8), p.935-940
Main Authors: Seehyun Kim, Wonyong Sung
Format: Article
Language:English
Subjects:
Analytical models
Discrete cosine transforms
Error analysis
Fixed-point arithmetic
Performance analysis
Quantization
Testing
Two dimensional displays
Very large scale integration
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Summary:Complete fixed-point error models that include the coefficient quantization are derived for two popular 8/spl times/8 two-dimensional (2-D) IDCT architectures; one is based on distributed arithmetic, and the other is the multiplier-adder chain. The error models are evaluated in the integer domain to accurately measure the effects of rounding. The analysis results show that the overall mean-square error performance (OMSE) is the most critical condition for meeting the IEEE specification (IEEE Std. 1180-1990) when the rounding scheme is employed. On the other hand, the mean error effects (OME and PME) are dominant for truncation. Finally, the analysis results are compared with those of bit-accurate simulation.
ISSN:1051-8215
1558-2205
DOI:10.1109/76.736720