A 260 MHz IF Sampling Bit-Stream Processing Digital Beamformer With an Integrated Array of Continuous-Time Band-Pass \Delta \Sigma Modulators

• Published in: IEEE journal of solid-state circuits 2016-05, Vol.51 (5), p.1168-1176
• Main Authors: Jaehun Jeong, Collins, Nicholas, Flynn, Michael P.
• Format: Article
• Language: English
• Subjects: Array signal processing; Arrays; Beamforming; bit-stream; delta-sigma; Digital signal processing; direct IF sampling; Modulation; Phase shifters; phased array; Prototypes; Receivers
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2015.2506645

We propose an ADC-digital codesign approach to IF sampling digital beamforming (DBF) that combines continuous-time bandpass ΔΣ modulators (CTBPDSMs) and bit-stream processing (BSP). This approach enables power-and area-efficient DBF by removing the need for digital multipliers and multiple decimators. The prototype beamformer digitizes eight 260 MHz IF signals at 1040 MS/s with eight CTBPDSMs, and performs digital down conversion and phase shifting with only multiplexers directly on the undecimated CTBPDSM outputs. With two sets of phase shifters, the prototype simultaneously forms two independent beams. Each phase shifter is controlled by a 12 bit programmable complex weight to provide a total of 240 phase-shift steps. By constructively combining inputs from eight elements, an 8.9 dB SNDR improvement is achieved, resulting in an array SNDR of 63.3 dB over a 10 MHz bandwidth. Fabricated in 65 nm CMOS, the eight-element two-beam prototype beamformer is the first IC implementation of IF sampling DBF. It occupies 0.28 mm 2 , and consumes 123.7 mW.