A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver

• Published in: IEEE journal of solid-state circuits 2016-04, Vol.51 (4), p.845-859
• Main Authors: Jiangfeng Wu, Cusmai, Giuseppe, Chou, Acer Wei-Te, Tao Wang, Bo Shen, Periasamy, Vijayaramalingam, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Kun Tan, Padyana, Aravind, Yang, Vincent Cheng-Hsun, Unruh, Gregory, Wong, Jackie Koon Lun, Hung, Bryan Juo-Jung, Brandolini, Massimo, Lin, Maco Sha-Ting, Xi Chen, Yen Ding, Yen-Jen Ko, Shin, Young J., Hung, Ada Hing T., Chen, Binning, Dang, Cynthia, Lakshminarasimhan, Deepak, Hong Liu, Lin, Jerry, Kowen Lai, Wassermann, Larry, Shrivastava, Ayaskant, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Krishnan, Lakshminarasimhan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Cangiane, Pete, Perlow, Randall, Ngai, William, Huang, Hanson Hung-Sen, Chang, James Y. C., Xicheng Jiang, Venes, Ardie, Gomez, Ramon Ray
• Format: Article
• Language: English
• Subjects: Analog-to-digital converter (ADC); Bandwidth; Cable modems; Cable TV; CMOS integrated circuits; Digital broadcasting; digital compensation; digital phase-locked loop (PLL); Digital signal processing; digital signal processing (DSP); digitally assisted analog; direct sampling; full-band capture (FBC); Gain; Phase locked loops; Receivers
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2015.2511164

A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing functionalities and enhancing performances, including digital automatic gain control (AGC), digital phase-locked loop (PLL), and digital ADC compensation. The receiver is capable of receiving 158 256 QAM channels from 48 to 1000 MHz simultaneously, achieving up to 10 Gb/s data throughput for data and video while exceeding Data over cable service interface specification (DOCSIS) and Society of Cable Telecommunications Engineers (SCTE) requirements. The CMOS receiver occupies 1 mm 2 area while consuming 300 mW. The LNA consumes 130 mW and occupies 3 mm 2 area. The total power dissipation from the receiver is 2.7 mW per 6 MHz channel when capturing the entire cable spectrum.