Challenges for the parallelization of loosely timed SystemC programs

SystemC/TLM models are commonly used in the industry to provide an early SoC simulation environment. The open source implementation of the SystemC simulator is sequential. The standard doesn't impose sequential executions, but makes this choice the easiest by imposing coroutine semantics. With...

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Bibliographic Details
Main Authors: Becker, Denis, Moy, Matthieu, Cornet, Jerome
Format: Conference Proceeding
Language:English
Subjects:
Computation
Computational modeling
Computer simulation
Hardware
Mathematical models
Parallel processing
Platforms
Prototyping
Semantics
Synchronization
Time-domain analysis
Time-varying systems
TLM model
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Summary:SystemC/TLM models are commonly used in the industry to provide an early SoC simulation environment. The open source implementation of the SystemC simulator is sequential. The standard doesn't impose sequential executions, but makes this choice the easiest by imposing coroutine semantics. With the increasing size and complexity of models, and the multiplication of computation cores on recent machines, the parallelization of SystemC simulations is a major research concern. There have been several proposals for SystemC parallelization, but most of them are limited to cycle-accurate models. In this paper we give an overview of the practices in one industrial context. We explain why loosely timed models are the only viable option in this context. We also show that unfortunately, most of the existing approaches for SystemC parallelization can fundamentally not apply to these models. We support this claim with a set of measurements performed on a platform used in production at STMicroelectronics. This paper both surveys existing techniques and identifies unsolved challenges in the parallelization of SystemC/TLM models.
ISSN:2150-5519
DOI:10.1109/RSP.2015.7416547