4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance

This paper describes design features of the high-performance CPU from a heterogeneous tri-cluster, deca-core CPU subsystem incorporated into the Helio X20 mobile SoC for smartphone applications. The SoC is fabricated in a 20nm high-κ metal-gate CMOS, and has a die size of 100mm2. Additional key feat...

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Main Authors: Mair, Hugh T., Gammie, Gordon, Wang, Alice, Lagerquist, Rolf, Chung, C. J., Gururajarao, Sumanth, Kao, Ping, Rajagopalan, Anand, Saha, Anirban, Jain, Amit, Wang, Ericbill, Ouyang, Shichin, Huajun Wen, Thippana, Achuta, HsinChen Chen, Rahman, Syed, Chau, Minh, Varma, Anshul, Flachs, Brian, Peng, Mark, Tsai, Alfred, Lin, Vincent, Ue Fu, Wuan Kuo, Lee-Kee Yong, Clavin Peng, Leo Shieh, Jengding Wu, Uming Ko
Format: Conference Proceeding
Language:English
Subjects:
Central Processing Unit
Clocks
Histograms
Mobile communication
Monitoring
Program processors
Voltage measurement
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Summary:This paper describes design features of the high-performance CPU from a heterogeneous tri-cluster, deca-core CPU subsystem incorporated into the Helio X20 mobile SoC for smartphone applications. The SoC is fabricated in a 20nm high-κ metal-gate CMOS, and has a die size of 100mm2. Additional key features of the SoC include: a graphics processor unit, multimedia (including 32MPixel/24fps camera support), and connectivity subsystems integrating 802.11ac, GPS, and multistandard cellular modems, featuring LTE FTD/TDD R11 Cat-6 with 20+20 carrier aggregation (300/50Mb/s) DC-HSPA+, TD-SCDMA, Edge, CDMA2000 1x/EVDO Rev. A (SRLTE).
ISSN:2376-8606
DOI:10.1109/ISSCC.2016.7417914