7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers

• Main Authors: Dongku Kang, Woopyo Jeong, Chulbum Kim, Doo-Hyun Kim, Yong Sung Cho, Kyung-Tae Kang, Jinho Ryu, Kyung-Min Kang, Sungyeon Lee, Wandong Kim, Hanjun Lee, Jaedoeg Yu, Nayoung Choi, Dong-Su Jang, Jeong-Don Ihm, Doogon Kim, Young-Sun Min, Moo-Sung Kim, An-Soo Park, Jae-Ick Son, In-Mo Kim, Pansuk Kwak, Bong-Kil Jung, Doo-Sub Lee, Hyunggon Kim, Hyang-Ja Yang, Dae-Seok Byeon, Ki-Tae Park, Kye-Hyun Kyung, Jeong-Hyuk Choi
• Format: Conference Proceeding
• Language: English
• Subjects: Computer architecture; Flash memories; Microprocessors; Reliability; Resistance; Temperature measurement; Temperature sensors
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2016.7417941

Today's explosive demand for data transfer is accelerating the development of non-volatile memory with even larger capacity and cheaper cost. Since the introduction of 3D technology in 2014 [1], V-NAND is believed to be a successful alternative to planar NAND and is quickly displacing planar NAND in the SSD market, due to its performance, reliability, and cost competitiveness. V-NAND has also eliminated the cell-to-cell interference problem by forming an atomic layer for charge trapping [2], which enables further technology scaling. However, the etching technology required for creating a channel hole cannot keep up with the market-driven WL stack requirement. Therefore, total mold height reduction is unavoidable and this creates several problems. 1) reduced mold height increases resistance and capacitance for WLs due to the thinner layers being used. 2) channel hole critical dimension (CD) variation becomes problematic because the additional mold stack height aggravates uniformity, thereby producing WL resistance variation. Consequently, read and program performance degradation is inevitable, furthermore their optimization becomes more challenging.