7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate

• Main Authors: Seungjae Lee, Jin-yub Lee, Il-han Park, Jongyeol Park, Sung-won Yun, Min-su Kim, Jong-hoon Lee, Minseok Kim, Kangbin Lee, Taeeun Kim, Byungkyu Cho, Dooho Cho, Sangbum Yun, Jung-no Im, Hyejin Yim, Kyung-hwa Kang, Suchang Jeon, Sungkyu Jo, Yang-lo Ahn, Sung-Min Joe, Suyong Kim, Deok-kyun Woo, Jiyoon Park, Hyun-wook Park, Youngmin Kim, Jonghoon Park, Yongsu Choi, Hirano, Makoto, Jeong-Don Ihm, Byunghoon Jeong, Seon-Kyoo Lee, Moosung Kim, Hokil Lee, Sungwhan Seo, Hongsoo Jeon, Chan-ho Kim, Hyunggon Kim, Jintae Kim, Yongsik Yim, Hoosung Kim, Dae-Seok Byeon, Hyang-Ja Yang, Ki-Tae Park, Kye-hyun Kyung, Jeong-Hyuk Choi
• Format: Conference Proceeding
• Language: English
• Subjects: CMOS integrated circuits; Flash memories; Performance evaluation; Programming; Resistance; Transistors; Very large scale integration
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2016.7417945

NAND flash memory is widely used as a cost-effective storage with high performance [1-2]. This paper presents a 128Gb multi-level cell (MLC) NAND flash memory with a 150 cells/string structure in 14nm CMOS that can be used as a cost-effective storage device. This paper also introduces several approaches to compensate for reliability and performance degradations caused by the 14nm transistors and the 150 cells/string structure. A technique was developed to suppress the background pattern dependency (BPD) by applying a low voltage to upper word lines (WLs) - the drain side(SSL side) WLs with respect to the location of the selected WL - during the verify sequence. Two techniques are also used to improve the program performance: equilibrium pulse scheme and smart start bias control scheme (SBC) in the MSB page. In addition, the first cycle recovery (FCR) of read enable (RE) and the bi-directional data strobe (DQS) is used to achieve a high speed I/O rate. As a result, a 640μs program time and a 800MB/s I/O rate is achieved.