A structured and scalable mechanism for test access to embedded reusable cores

The main objective of core-based IC design is improvement of design efficiency and time-to-market. In order to prevent test development from becoming the bottleneck in the entire development trajectory, reuse of pre-computed tests for the reusable pre-designed cores is mandatory. The core user is re...

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Bibliographic Details
Main Authors: Marinissen, E.J., Arendsen, R., Bos, G., Dingemanse, H., Lousberg, M., Wouters, C.
Format: Conference Proceeding
Language:English
Subjects:
Automatic testing
Circuit testing
Integrated circuit testing
Intellectual property
Laboratories
Pins
Process design
Semiconductor device testing
System testing
Time to market
Online Access:Request full text
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Summary:The main objective of core-based IC design is improvement of design efficiency and time-to-market. In order to prevent test development from becoming the bottleneck in the entire development trajectory, reuse of pre-computed tests for the reusable pre-designed cores is mandatory. The core user is responsible for translating the test at core level into a test at chip level. A standardized test access mechanism eases this task, therefore contributing to the plug-n-play character of core-based design. This paper presents the concept of a structured test access mechanism for embedded cores. Reusable IP modules are wrapped in a TESTSHELL. Test data access from chip pins to TESTSHELL and vice versa is provided by the TESTRAIL, while the operation of the TESTSHELL is controlled by a dedicated test control mechanism (TCM). Both TESTRAIL as well as TCM are standardized, but open for extensions.
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.1998.743166