Implicit test generation for behavioral VHDL models

This paper proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions. The proposed approach is based on the comparison between the implicit description of the fault-free behavior and the faulty behavior, obtained through a new behavioral fault model. The paper wi...

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Bibliographic Details
Main Authors: Ferrandi, F., Fummi, F., Sciuto, D.
Format: Conference Proceeding
Language:English
Subjects:
Automata
Circuit faults
Circuit testing
Electronic design automation and methodology
Fault diagnosis
Guidelines
High level synthesis
Logic testing
Performance evaluation
Test pattern generators
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Description
Summary:This paper proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions. The proposed approach is based on the comparison between the implicit description of the fault-free behavior and the faulty behavior, obtained through a new behavioral fault model. The paper will experimentally show that the test patterns generated at the behavioral level provide a very high stuck-at fault coverage when applied to different gate-level implementations of the given VHDL behavioral specification. Gate-level ATPGs applied on these same circuits obtain lower fault coverage, in particular when considering circuits with hard to detect faults.
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.1998.743202