VLSI architecture for coherent 9/7 lifting based 2D-discrete wavelet transform

• Main Authors: Maye, G. Kiran, Srinivasulu, T.
• Format: Conference Proceeding
• Language: English
• Subjects: Adders; Architecture; area; Clocks; Coherence; Discrete wavelet transform; Discrete wavelet transforms; Electronics; Field programmable gate arrays; FPGA; Hardware; Hoisting; Image coding; Performance enhancement; power consumption; Scanning; Utilization; VLSI; Wavelet transforms; word length; Xilinx
• ISSN: 2325-9418
• DOI: 10.1109/INDICON.2015.7443121

In this paper we propose architecture to decrease the area utilization and improve the performance. To decrease the area utilization, a coherent 2D-DWT lifting based 9/7 wavelet is designed which also improves the performance. A coherent 2D-DWT method employed overlapped-stripe based scanning and stripe-based scanning for scanning the suitable inputs, so that temporal memory will get decreased. Usually the 2D-DWT operation is made in two level, in the initial level there is one predict step and update step, the second level in addition have the similar step repetitively. However, these two levels is made simpler and executed in a single level in coherent 2D-DWT, thus the area and power will very much decreased and the performance furthermore get enhanced. The architecture is parameterized to deal with different images and word length sizes. By means of a Virtex 4 Xilinx ISE 14.1 FPGA platform the suggested architecture is executed. The execution results expose that the suggested architecture is enhanced in area competence of 1% slices, 1% of DSP 48s, multipliers and adders are also decreased.