Impulse: building a smarter memory controller

• Main Authors: Carter, J., Hsieh, W., Stoller, L., Swanson, M., Lixin Zhang, Brunvand, E., Davis, A., Chen-Chi Kuo, Kuramkote, R., Parker, M., Schaelicke, L., Tateyama, T.
• Format: Conference Proceeding
• Language: English
• Subjects: Bandwidth; Cities and towns; Computer science; Delay; Electronic switching systems; Microprocessors; Prefetching; Random access memory; Sparse matrices
• DOI: 10.1109/HPCA.1999.744334

Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and cached, improving their cache and bus utilization. Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses. In this paper we describe the design of the Impulse architecture, and show how an Impulse memory system can be used to improve the performance of memory-bound programs. For the NAS conjugate gradient benchmark, Impulse improves performance by 67%. Because it requires no modification to processor, cache, or bus designs, Impulse can be adopted in conventional systems. In addition to scientific applications, we expect that Impulse will benefit regularly strided memory-bound applications of commercial importance, such as database and multimedia programs.