Transistor matching in analog CMOS applications

This paper gives an overview of MOSFET mismatch effects that form a performance/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design...

Full description

Saved in:
Bibliographic Details
Main Authors: Pelgrom, M.J.M., Tuinhout, H.P., Vertregt, M.
Format: Conference Proceeding
Language:English
Subjects:
Analog circuits
Analog-digital conversion
Clocks
Design automation
Doping
Laboratories
MOSFET circuits
Multiplexing
Neodymium
Threshold voltage
Citations: Items that cite this one
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by cdi_FETCH-LOGICAL-c285t-94c811d570e8c406ec2525da75100f77aadc7ded06b34348a98f72467d9b61553
cites
container_end_page 918
container_issue
container_start_page 915
container_title
container_volume
creator Pelgrom, M.J.M.
Tuinhout, H.P.
Vertregt, M.
description This paper gives an overview of MOSFET mismatch effects that form a performance/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease.
doi_str_mv 10.1109/IEDM.1998.746503
format conference_proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_746503</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>746503</ieee_id><sourcerecordid>746503</sourcerecordid><originalsourceid>FETCH-LOGICAL-c285t-94c811d570e8c406ec2525da75100f77aadc7ded06b34348a98f72467d9b61553</originalsourceid><addsrcrecordid>eNotz7tOwzAUgGGLi0Ra2BFTXiDpOb4de0SlQKVWHSgSW-XaTjFKkyjOwtszlOnfPuln7BGhRgS7WK9etjVaa2qSWoG4YgVHpStA-rpmMyADQhJJe8MKQC0qtGju2CznHwBOyqqCLfaj63LKUz-WZzf579SdytSVrnNtfyqX291H6YahTd5Nqe_yPbttXJvjw3_n7PN1tV--V5vd23r5vKk8N2qqrPQGMSiCaLwEHT1XXAVHCgEaIueCpxAD6KOQQhpnTUNcagr2qFEpMWdPFzfFGA_DmM5u_D1cPsUfEXlDdQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Transistor matching in analog CMOS applications</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Pelgrom, M.J.M. ; Tuinhout, H.P. ; Vertregt, M.</creator><creatorcontrib>Pelgrom, M.J.M. ; Tuinhout, H.P. ; Vertregt, M.</creatorcontrib><description>This paper gives an overview of MOSFET mismatch effects that form a performance/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease.</description><identifier>ISSN: 0163-1918</identifier><identifier>ISBN: 0780347749</identifier><identifier>ISBN: 9780780347748</identifier><identifier>EISSN: 2156-017X</identifier><identifier>DOI: 10.1109/IEDM.1998.746503</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analog circuits ; Analog-digital conversion ; Clocks ; Design automation ; Doping ; Laboratories ; MOSFET circuits ; Multiplexing ; Neodymium ; Threshold voltage</subject><ispartof>International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), 1998, p.915-918</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c285t-94c811d570e8c406ec2525da75100f77aadc7ded06b34348a98f72467d9b61553</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/746503$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/746503$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Pelgrom, M.J.M.</creatorcontrib><creatorcontrib>Tuinhout, H.P.</creatorcontrib><creatorcontrib>Vertregt, M.</creatorcontrib><title>Transistor matching in analog CMOS applications</title><title>International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)</title><addtitle>IEDM</addtitle><description>This paper gives an overview of MOSFET mismatch effects that form a performance/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease.</description><subject>Analog circuits</subject><subject>Analog-digital conversion</subject><subject>Clocks</subject><subject>Design automation</subject><subject>Doping</subject><subject>Laboratories</subject><subject>MOSFET circuits</subject><subject>Multiplexing</subject><subject>Neodymium</subject><subject>Threshold voltage</subject><issn>0163-1918</issn><issn>2156-017X</issn><isbn>0780347749</isbn><isbn>9780780347748</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1998</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotz7tOwzAUgGGLi0Ra2BFTXiDpOb4de0SlQKVWHSgSW-XaTjFKkyjOwtszlOnfPuln7BGhRgS7WK9etjVaa2qSWoG4YgVHpStA-rpmMyADQhJJe8MKQC0qtGju2CznHwBOyqqCLfaj63LKUz-WZzf579SdytSVrnNtfyqX291H6YahTd5Nqe_yPbttXJvjw3_n7PN1tV--V5vd23r5vKk8N2qqrPQGMSiCaLwEHT1XXAVHCgEaIueCpxAD6KOQQhpnTUNcagr2qFEpMWdPFzfFGA_DmM5u_D1cPsUfEXlDdQ</recordid><startdate>1998</startdate><enddate>1998</enddate><creator>Pelgrom, M.J.M.</creator><creator>Tuinhout, H.P.</creator><creator>Vertregt, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>1998</creationdate><title>Transistor matching in analog CMOS applications</title><author>Pelgrom, M.J.M. ; Tuinhout, H.P. ; Vertregt, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c285t-94c811d570e8c406ec2525da75100f77aadc7ded06b34348a98f72467d9b61553</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Analog circuits</topic><topic>Analog-digital conversion</topic><topic>Clocks</topic><topic>Design automation</topic><topic>Doping</topic><topic>Laboratories</topic><topic>MOSFET circuits</topic><topic>Multiplexing</topic><topic>Neodymium</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Pelgrom, M.J.M.</creatorcontrib><creatorcontrib>Tuinhout, H.P.</creatorcontrib><creatorcontrib>Vertregt, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Pelgrom, M.J.M.</au><au>Tuinhout, H.P.</au><au>Vertregt, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Transistor matching in analog CMOS applications</atitle><btitle>International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)</btitle><stitle>IEDM</stitle><date>1998</date><risdate>1998</risdate><spage>915</spage><epage>918</epage><pages>915-918</pages><issn>0163-1918</issn><eissn>2156-017X</eissn><isbn>0780347749</isbn><isbn>9780780347748</isbn><abstract>This paper gives an overview of MOSFET mismatch effects that form a performance/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease.</abstract><pub>IEEE</pub><doi>10.1109/IEDM.1998.746503</doi><tpages>4</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0163-1918
ispartof International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), 1998, p.915-918
issn 0163-1918
2156-017X
language eng
recordid cdi_ieee_primary_746503
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Analog circuits
Analog-digital conversion
Clocks
Design automation
Doping
Laboratories
MOSFET circuits
Multiplexing
Neodymium
Threshold voltage
title Transistor matching in analog CMOS applications
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T03%3A09%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Transistor%20matching%20in%20analog%20CMOS%20applications&rft.btitle=International%20Electron%20Devices%20Meeting%201998.%20Technical%20Digest%20(Cat.%20No.98CH36217)&rft.au=Pelgrom,%20M.J.M.&rft.date=1998&rft.spage=915&rft.epage=918&rft.pages=915-918&rft.issn=0163-1918&rft.eissn=2156-017X&rft.isbn=0780347749&rft.isbn_list=9780780347748&rft_id=info:doi/10.1109/IEDM.1998.746503&rft_dat=%3Cieee_6IE%3E746503%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c285t-94c811d570e8c406ec2525da75100f77aadc7ded06b34348a98f72467d9b61553%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=746503&rfr_iscdi=true