Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory

In this letter, we propose a layer selection method by permutations (LSMPs) of string select line (SSL) bias and string select transistor with multi-level states. Due to the increased number of threshold voltage orderings by the permutation, the number of required SSLs for the layer selection and th...

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Bibliographic Details
Published in:IEEE electron device letters 2016-07, Vol.37 (7), p.866-869
Main Authors: Lee, Sang-Ho, Kim, Wandong, Kwon, Dae Woong, Seo, Joo Yun, Baek, Myung Hyun, Lee, Sungbok, Kang, Jinkyu, Jang, Woojae, Lee, Jong-Ho, Park, Byung-Gook
Format: Article
Language:English
Subjects:
3D NAND flash memory
electrical initialization
Equivalent circuits
Flash memories
layer selection
Logic gates
LSM
LSMP
permutation
Silicon
Three-dimensional displays
Threshold voltage
Very large scale integration
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Summary:In this letter, we propose a layer selection method by permutations (LSMPs) of string select line (SSL) bias and string select transistor with multi-level states. Due to the increased number of threshold voltage orderings by the permutation, the number of required SSLs for the layer selection and the space occupied by SSLs can be minimized. Also, the operation scheme for the layer selection is discussed. To verify the operation of proposed LSMP, a fabricated pseudo-LSM is measured. As a result, it is clearly revealed that the number of selectable layer can be increased drastically by the LSMP.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2016.2568171