A 2.3-mW 0.01-mm ^} 1.25-GHz Quadrature Signal Corrector With 1.1-ps Error for Mobile DRAM Interface in 65-nm CMOS

In this brief, we propose a quadrature signal corrector for a low-power DDR4 mobile DRAM interface. In order to eliminate the phase imbalance among quadrature signals, the proposed architecture employs digitally controlled delay lines in a shared digital feedback loop with a time-multiplexed loop fi...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2017-04, Vol.64 (4), p.397-401
Main Authors: Kim, YongJo, Song, Keunsoo, Kim, Dongkyun, Cho, SeongHwan
Format: Article
Language:English
Subjects:
Bang–bang phase detector (BBPD)
Computer architecture
Delays
digitally controlled delay line (DCDL)
Feedback loop
Logic gates
Multiplexing
quadrature clock signal corrector
time-multiplexed loop filter
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Summary:In this brief, we propose a quadrature signal corrector for a low-power DDR4 mobile DRAM interface. In order to eliminate the phase imbalance among quadrature signals, the proposed architecture employs digitally controlled delay lines in a shared digital feedback loop with a time-multiplexed loop filter so as to minimize the effect of circuit mismatch that hampers the phase accuracy. A self-calibrated offset delay is also proposed, which allows the use of a simple 1-bit TDC instead of a power-hungry wide-dynamic range TDC. Implemented in 65-nm CMOS, the prototype chip achieves less than 1.1-ps phase error for a 1.25-GHz quadrature signal and occupies an active area of only 0.01 mm 2 while consuming 2.27 mW from a 1.0-V supply.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2016.2569441