Efficient deblocking filter implementation on reconfigurable processor

As world is moving towards Ultra High Definition (UHD) content and display technology, high quality visual content is becoming a necessity. Deblocking filter is one of the tools used in today's video coding standards to enhance the quality of compressed video. Deblocking consumes significant pe...

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Bibliographic Details
Main Authors: Maiti, Kausik, Pasupuleti, Sirish K., Gadde, Raj N., Sang Jo Lee
Format: Conference Proceeding
Language:English
Subjects:
Catering
Coding
Deblocking
Decision support systems
Electronics
Hardware
HEVC
High definition
Indexes
Microprocessors
Reconfigurable processor
Video compression
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Summary:As world is moving towards Ultra High Definition (UHD) content and display technology, high quality visual content is becoming a necessity. Deblocking filter is one of the tools used in today's video coding standards to enhance the quality of compressed video. Deblocking consumes significant percentage (~20%-33%) of total decoding cycles. Therefore, many decoder implementations tend to offload deblocking operation to additional hardware IP block or GPU to achieve real-time performance. However, hardware IP increases die area and lacks flexibility; on other hand GPUs are power hungry. In this paper, we present a reconfigurable processor based software solution along with a deblocking specific intrinsic catering to wide range of video coding standards for handling this performance bottleneck. Our experimental results show, proposed approach improves deblocking performance by a factor greater than 10 and results in processing time in the order of 140 ms for 4K UHD HEVC (60 fps, 30 mbps) stream.
ISSN:2379-190X
DOI:10.1109/ICASSP.2016.7471836