Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results

With CMOS technology scaling, it becomes more and more difficult to guarantee circuit functionality for all process, voltage, temperature (PVT) corners. Moreover, circuit wear-out degradation lead to additional temporal variations, resulting in an important increase of design margins when targeting...

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Bibliographic Details
Main Authors: Anghel, Lorena, Benhassain, A., Sivadasan, A., Cacho, F., Huard, V.
Format: Conference Proceeding
Language:English
Subjects:
Aging
Circuit design
Corners
Crashworthiness
Degradation
Electric potential
Integrated circuit reliability
Monitoring
Monitors
Temperature measurement
Temperature sensors
Timing
Very large scale integration
VTS
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Summary:With CMOS technology scaling, it becomes more and more difficult to guarantee circuit functionality for all process, voltage, temperature (PVT) corners. Moreover, circuit wear-out degradation lead to additional temporal variations, resulting in an important increase of design margins when targeting specific reliable systems (automotive or health care embedded applications) [1]. Adding pessimistic timing margin to guarantee all operating points under worse case conditions is no more acceptable due to the huge impact on design costs, such as up to 10% increase of slack time, with an upward trend as technology moves further.
ISSN:2375-1053
DOI:10.1109/VTS.2016.7477316