A 5-GHz inductor-noise cancelling receiver with 1.8 dB noise figure in 65nm LP CMOS

In this paper, a novel receiver architecture with inductor-noise cancellation technique is presented. The proposed receiver employs two separate down-conversion paths driven by I/Q LOs respectively, and the noise of on-chip gate inductor of common-source LNA is cancelled at the baseband output, with...

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Bibliographic Details
Main Authors: Qin, Chuan, Zhang, Lei, Pan, Zhijian, Zhang, Li, Wang, Yan, Yu, Zhiping
Format: Conference Proceeding
Language:English
Subjects:
Architecture
Arts
Cancellation
CMOS
CMOS integrated circuits
current-mode
inductor-noise cancelling
Inductors
Logic gates
Noise
Noise cancellation
noise figure
Noise levels
Noise measurement
Power consumption
Receiver
Receivers
Wideband
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Summary:In this paper, a novel receiver architecture with inductor-noise cancellation technique is presented. The proposed receiver employs two separate down-conversion paths driven by I/Q LOs respectively, and the noise of on-chip gate inductor of common-source LNA is cancelled at the baseband output, without additional penalty on power consumption, while the signal is in-phase and strengthened. The noise figure is therefore significantly improved versus prior arts. A demo 5-GHz receiver employing the proposed architecture is designed and implemented in a 65-nm low power CMOS process. Measured result shows a noise figure of 1.8 dB at 5 GHz band, while consuming only 95 mW of power from a 1.2 V supply.
ISSN:2375-0995
DOI:10.1109/RFIC.2016.7508256