Loading…

Process-Induced Variations of 10-nm Node Bulk nFinFETs Considering Middle-of-Line Parasitics

Process-induced variations of 10-nm node n-type FinFETs considering middle-of-line parasitics were investigated in terms of dc/ac performances using fully calibrated TCAD simulations. Variations of positive fixed oxide charge density at shallow trench isolation interface and source/drain (S/D) heigh...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on electron devices 2016-09, Vol.63 (9), p.3399-3405
Main Authors: Yoon, Jun-Sik, Baek, Chang-Ki, Baek, Rock-Hyun
Format: Article
Language:English
Subjects:
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Process-induced variations of 10-nm node n-type FinFETs considering middle-of-line parasitics were investigated in terms of dc/ac performances using fully calibrated TCAD simulations. Variations of positive fixed oxide charge density at shallow trench isolation interface and source/drain (S/D) height influenced off-state and on-state performance variations, respectively, but slightly on RC delay variations. Fin width variations induced off-state performance and RC delay variations critically due to the fluctuation of short channel effects. But, fin height variations affected them slightly due to the preserved gate-to-channel controllability and the buffered effects by varying drain currents and gate capacitances in the same direction. Gate length, spacer length, and S/D length variations influenced dc/ac performance variations severely; 2-nm-length changes were barely acceptable to satisfy 10% RC delay margin. Thus, the process-induced variability parameters, including fin width, gate length, spacer length, and S/D length, should be controlled tightly under a few nanometers to reduce dc/ac performance variations of the FinFETs.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2016.2586505