Architectural yield optimization for WSI

A novel methodology for investigating wafer-scale integration (WSI) designs is proposed. This methodology combines the results of work on integrated circuit yield modeling with a study of the effects of system architecture in large-area integrated circuit yield. This work provides a hierarchical fra...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on computers 1988-01, Vol.37 (1), p.88-110
Main Authors: Harden, J.C., Stader, N.R.
Format: Article
Language:English
Subjects:
Applied sciences
Binary trees
Circuit faults
Electronics
Exact sciences and technology
Hardware
Integrated circuit modeling
Integrated circuit packaging
Integrated circuit yield
Optimization methods
Redundancy
Reliability
Semiconductor device modeling
Semiconductor device packaging
Very large scale integration
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A novel methodology for investigating wafer-scale integration (WSI) designs is proposed. This methodology combines the results of work on integrated circuit yield modeling with a study of the effects of system architecture in large-area integrated circuit yield. This work provides a hierarchical framework in which computing structures may be analyzed to determine functionality on a wafer scale and develops methods by which this functionality can be optimized.< >
ISSN:0018-9340
1557-9956
DOI:10.1109/12.75138