Architectural yield optimization for WSI

A novel methodology for investigating wafer-scale integration (WSI) designs is proposed. This methodology combines the results of work on integrated circuit yield modeling with a study of the effects of system architecture in large-area integrated circuit yield. This work provides a hierarchical fra...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on computers 1988-01, Vol.37 (1), p.88-110
Main Authors: Harden, J.C., Stader, N.R.
Format: Article
Language:English
Subjects:
Applied sciences
Binary trees
Circuit faults
Electronics
Exact sciences and technology
Hardware
Integrated circuit modeling
Integrated circuit packaging
Integrated circuit yield
Optimization methods
Redundancy
Reliability
Semiconductor device modeling
Semiconductor device packaging
Very large scale integration
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by cdi_FETCH-LOGICAL-c303t-984c8c6f98e1671ddc9cb7ffd3a9482259e5f63132b8e0aaed84aeead9e2849a3
cites cdi_FETCH-LOGICAL-c303t-984c8c6f98e1671ddc9cb7ffd3a9482259e5f63132b8e0aaed84aeead9e2849a3
container_end_page 110
container_issue 1
container_start_page 88
container_title IEEE transactions on computers
container_volume 37
creator Harden, J.C.
Stader, N.R.
description A novel methodology for investigating wafer-scale integration (WSI) designs is proposed. This methodology combines the results of work on integrated circuit yield modeling with a study of the effects of system architecture in large-area integrated circuit yield. This work provides a hierarchical framework in which computing structures may be analyzed to determine functionality on a wafer scale and develops methods by which this functionality can be optimized.< >
doi_str_mv 10.1109/12.75138
format article
fullrecord <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_ieee_primary_75138</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>75138</ieee_id><sourcerecordid>28564214</sourcerecordid><originalsourceid>FETCH-LOGICAL-c303t-984c8c6f98e1671ddc9cb7ffd3a9482259e5f63132b8e0aaed84aeead9e2849a3</originalsourceid><addsrcrecordid>eNpF0D1LA0EQh_FFFIxRsLW7QiTNxZ19udstg_gSCFioWC6TvVlcueTi7qWIn96YBK2mmB9P8WfsEvgYgNtbEONagzRHbABa16W1ujpmA87BlFYqfsrOcv7knFeC2wEbTZL_iD35fp2wLTaR2qboVn1cxG_sY7csQpeK95fpOTsJ2Ga6ONwhe3u4f717KmfPj9O7yaz0ksu-tEZ546tgDUFVQ9N46-d1CI1Eq4wQ2pIOlQQp5oY4IjVGIRE2loRRFuWQ3ey7q9R9rSn3bhGzp7bFJXXr7ITRlRKgtnC0hz51OScKbpXiAtPGAXe_UzgQbjfFll4fmpg9tiHh0sf852sDVnK9ZVd7Fono_7tL_ACH2mSz</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>28564214</pqid></control><display><type>article</type><title>Architectural yield optimization for WSI</title><source>IEEE Xplore (Online service)</source><creator>Harden, J.C. ; Stader, N.R.</creator><creatorcontrib>Harden, J.C. ; Stader, N.R.</creatorcontrib><description>A novel methodology for investigating wafer-scale integration (WSI) designs is proposed. This methodology combines the results of work on integrated circuit yield modeling with a study of the effects of system architecture in large-area integrated circuit yield. This work provides a hierarchical framework in which computing structures may be analyzed to determine functionality on a wafer scale and develops methods by which this functionality can be optimized.&lt; &gt;</description><identifier>ISSN: 0018-9340</identifier><identifier>EISSN: 1557-9956</identifier><identifier>DOI: 10.1109/12.75138</identifier><identifier>CODEN: ITCOB4</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Binary trees ; Circuit faults ; Electronics ; Exact sciences and technology ; Hardware ; Integrated circuit modeling ; Integrated circuit packaging ; Integrated circuit yield ; Optimization methods ; Redundancy ; Reliability ; Semiconductor device modeling ; Semiconductor device packaging ; Very large scale integration</subject><ispartof>IEEE transactions on computers, 1988-01, Vol.37 (1), p.88-110</ispartof><rights>1988 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c303t-984c8c6f98e1671ddc9cb7ffd3a9482259e5f63132b8e0aaed84aeead9e2849a3</citedby><cites>FETCH-LOGICAL-c303t-984c8c6f98e1671ddc9cb7ffd3a9482259e5f63132b8e0aaed84aeead9e2849a3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/75138$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,4024,27923,27924,27925,54796</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&amp;idt=7819305$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Harden, J.C.</creatorcontrib><creatorcontrib>Stader, N.R.</creatorcontrib><title>Architectural yield optimization for WSI</title><title>IEEE transactions on computers</title><addtitle>TC</addtitle><description>A novel methodology for investigating wafer-scale integration (WSI) designs is proposed. This methodology combines the results of work on integrated circuit yield modeling with a study of the effects of system architecture in large-area integrated circuit yield. This work provides a hierarchical framework in which computing structures may be analyzed to determine functionality on a wafer scale and develops methods by which this functionality can be optimized.&lt; &gt;</description><subject>Applied sciences</subject><subject>Binary trees</subject><subject>Circuit faults</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Hardware</subject><subject>Integrated circuit modeling</subject><subject>Integrated circuit packaging</subject><subject>Integrated circuit yield</subject><subject>Optimization methods</subject><subject>Redundancy</subject><subject>Reliability</subject><subject>Semiconductor device modeling</subject><subject>Semiconductor device packaging</subject><subject>Very large scale integration</subject><issn>0018-9340</issn><issn>1557-9956</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1988</creationdate><recordtype>article</recordtype><recordid>eNpF0D1LA0EQh_FFFIxRsLW7QiTNxZ19udstg_gSCFioWC6TvVlcueTi7qWIn96YBK2mmB9P8WfsEvgYgNtbEONagzRHbABa16W1ujpmA87BlFYqfsrOcv7knFeC2wEbTZL_iD35fp2wLTaR2qboVn1cxG_sY7csQpeK95fpOTsJ2Ga6ONwhe3u4f717KmfPj9O7yaz0ksu-tEZ546tgDUFVQ9N46-d1CI1Eq4wQ2pIOlQQp5oY4IjVGIRE2loRRFuWQ3ey7q9R9rSn3bhGzp7bFJXXr7ITRlRKgtnC0hz51OScKbpXiAtPGAXe_UzgQbjfFll4fmpg9tiHh0sf852sDVnK9ZVd7Fono_7tL_ACH2mSz</recordid><startdate>198801</startdate><enddate>198801</enddate><creator>Harden, J.C.</creator><creator>Stader, N.R.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>198801</creationdate><title>Architectural yield optimization for WSI</title><author>Harden, J.C. ; Stader, N.R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c303t-984c8c6f98e1671ddc9cb7ffd3a9482259e5f63132b8e0aaed84aeead9e2849a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1988</creationdate><topic>Applied sciences</topic><topic>Binary trees</topic><topic>Circuit faults</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Hardware</topic><topic>Integrated circuit modeling</topic><topic>Integrated circuit packaging</topic><topic>Integrated circuit yield</topic><topic>Optimization methods</topic><topic>Redundancy</topic><topic>Reliability</topic><topic>Semiconductor device modeling</topic><topic>Semiconductor device packaging</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Harden, J.C.</creatorcontrib><creatorcontrib>Stader, N.R.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Harden, J.C.</au><au>Stader, N.R.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Architectural yield optimization for WSI</atitle><jtitle>IEEE transactions on computers</jtitle><stitle>TC</stitle><date>1988-01</date><risdate>1988</risdate><volume>37</volume><issue>1</issue><spage>88</spage><epage>110</epage><pages>88-110</pages><issn>0018-9340</issn><eissn>1557-9956</eissn><coden>ITCOB4</coden><abstract>A novel methodology for investigating wafer-scale integration (WSI) designs is proposed. This methodology combines the results of work on integrated circuit yield modeling with a study of the effects of system architecture in large-area integrated circuit yield. This work provides a hierarchical framework in which computing structures may be analyzed to determine functionality on a wafer scale and develops methods by which this functionality can be optimized.&lt; &gt;</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/12.75138</doi><tpages>23</tpages></addata></record>
fulltext fulltext
identifier ISSN: 0018-9340
ispartof IEEE transactions on computers, 1988-01, Vol.37 (1), p.88-110
issn 0018-9340
1557-9956
language eng
recordid cdi_ieee_primary_75138
source IEEE Xplore (Online service)
subjects Applied sciences
Binary trees
Circuit faults
Electronics
Exact sciences and technology
Hardware
Integrated circuit modeling
Integrated circuit packaging
Integrated circuit yield
Optimization methods
Redundancy
Reliability
Semiconductor device modeling
Semiconductor device packaging
Very large scale integration
title Architectural yield optimization for WSI
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T17%3A18%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Architectural%20yield%20optimization%20for%20WSI&rft.jtitle=IEEE%20transactions%20on%20computers&rft.au=Harden,%20J.C.&rft.date=1988-01&rft.volume=37&rft.issue=1&rft.spage=88&rft.epage=110&rft.pages=88-110&rft.issn=0018-9340&rft.eissn=1557-9956&rft.coden=ITCOB4&rft_id=info:doi/10.1109/12.75138&rft_dat=%3Cproquest_ieee_%3E28564214%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c303t-984c8c6f98e1671ddc9cb7ffd3a9482259e5f63132b8e0aaed84aeead9e2849a3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=28564214&rft_id=info:pmid/&rft_ieee_id=75138&rfr_iscdi=true