Real-Time Computing on Multicore Processors

Architects of multicore chips for avionics must define and bound intercore interference, which requires assuming a constant worst-case execution time for tasks executing on the chip. With the Single Core Equivalent technology package, engineers can treat each core as if it were a single-core chip.

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Bibliographic Details
Published in:Computer (Long Beach, Calif.) Calif.), 2016-09, Vol.49 (9), p.69-77
Main Authors: Lui Sha, Caccamo, Marco, Mancuso, Renato, Jung-Eun Kim, Man-Ki Yoon, Pellizzoni, Rodolfo, Heechul Yun, Kegley, Russell B., Perlman, Dennis R., Arundale, Greg, Bradford, Richard
Format: Article
Language:English
Subjects:
Avionics
avionics computing
Computer engineering
Engineers
Memory access
memory-access conflicts
multicore architecture
multicore chips
Multicore processing
Real-time systems
Semiconductors
Single core equivalence
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Description
Summary:Architects of multicore chips for avionics must define and bound intercore interference, which requires assuming a constant worst-case execution time for tasks executing on the chip. With the Single Core Equivalent technology package, engineers can treat each core as if it were a single-core chip.
ISSN:0018-9162
1558-0814
DOI:10.1109/MC.2016.271