An Iterative Logarithmic Multiplier with Improved Precision

Recent studies have demonstrated the potential for achieving higher area and power saving with approximate computation in error tolerant applications involving signal and image processing. Multiplication is a major mathematical operation in these applications which when performed in logarithmic numb...

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Bibliographic Details
Main Authors: Ahmed, Syed Ershad, Kadam, Sanket, Srinivas, M. B.
Format: Conference Proceeding
Language:English
Subjects:
Adders
Computer architecture
Decoding
Error correction
Hardware
Iterative methods
Iterative Multiplier
Logarithmic Number System
Logarithmic Shifter
Mathematical model
Mitchell Algorithm
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Summary:Recent studies have demonstrated the potential for achieving higher area and power saving with approximate computation in error tolerant applications involving signal and image processing. Multiplication is a major mathematical operation in these applications which when performed in logarithmic number system results in faster and energy efficient design. In this paper, the authors present a method which combines the Mitchell's approximation and hardware truncation scheme in a novel way resulting in an iterative multiplier with improved precision and area. Further, proposed truncation approach and fractional predictor significantly reduce the overall hardware requirement of the multiplier. Experimental results prove the superiority of the proposed multiplier over previous designs.
ISSN:1063-6889
DOI:10.1109/ARITH.2016.25