Transistor reliability characterization and comparisons for a 14 nm tri-gate technology optimized for System-on-Chip and foundry platforms

• Main Authors: Prasad, C., Park, K. W., Chahal, M., Meric, I., Novak, S. R., Ramey, S., Bai, P., Chang, H.-Y, Dias, N. L., Hafez, W. M., Jan, C.-H, Nidhi, N., Olac-vaw, R. W., Ramaswamy, R., Tsai, C.
• Format: Conference Proceeding
• Language: English
• Subjects: CMOS Process; Degradation; Dielectrics; Integrated circuit reliability; Logic gates; MOS devices; Reliability; Semiconductor Device Reliability; System-on-chip; Transistor; Transistors
• ISSN: 1938-1891
• DOI: 10.1109/IRPS.2016.7574536

The transistor reliability characterization of a 14nm System-on-Chip (SoC) node optimized for low power operation is described. In-depth assessments of reliability and performance for Core and I/O devices are performed on Logic and SoC nodes, and clear trends with scaling are identified. Insight is provided into hot carrier and off-state aging, and self-heat effects. Technological advancements across process nodes demonstrate the ability to achieve matched or improved reliability in conjunction with robust generational performance gains. The 14nm SoC node is shown to be robust for all transistor reliability modes. Process monitor data are used to demonstrate the stability of the production line in high-volume manufacturing.