Optimization of PESD implant design for ESD robustness of 5V drain-back N-LDMOSFET

An N-LDMOS ESD protection device with drain back and PESD optimization design is proposed. With PESD layer enclosing the N+ drain region, a parasitic SCR is created to achieve high ESD level. When PESD is close to gate, the turn-on efficiency can be further improved (Vt1: 11.2 V reduced to 7.2 V) by...

Full description

Saved in:
Bibliographic Details
Main Authors: Chun Chiang, Ping-Chen Chang, Pei-Shan Tseng, Po-Ya Lai, Tien-Hao Tang, Kuan-Cheng Su
Format: Conference Proceeding
Language:English
Subjects:
Breakdown voltage
Current distribution
DEMOS
Drain back
Electrostatic discharges
HBM
Implants
LDMOS
Logic gates
PESD
Pull back
SCR
TCAD simulation
Thyristors
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:An N-LDMOS ESD protection device with drain back and PESD optimization design is proposed. With PESD layer enclosing the N+ drain region, a parasitic SCR is created to achieve high ESD level. When PESD is close to gate, the turn-on efficiency can be further improved (Vt1: 11.2 V reduced to 7.2 V) by the punch-through path from N + /PESD to PW. The proposed ESD N-LDMOS can sustain over 8KV HBM with low trigger behavior without extra area cost.
ISSN:1938-1891
DOI:10.1109/IRPS.2016.7574604