Trimodal Scan-Based Test Paradigm

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2017-03, Vol.25 (3), p.1112-1125
• Main Authors: Mrugalski, Grzegorz, Rajski, Janusz, Solecki, Jedrzej, Tyszer, Jerzy, Chen Wang
• Format: Article
• Language: English
• Subjects: Built-in self-test; Circuit faults; Clocks; Computer architecture; Design for testability; Discrete Fourier transforms; low-power test; Registers; scan-based testing; test application time; test data compression; test-per-clock scheme
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2016.2608984

This paper presents a novel scan-based design for test (DFT) paradigm. Compared with conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage or allows applying a much larger number of vectors within the same time interval. An equally important factor is the toggling activity during test-with this scheme, it remains similar to that of the mission mode. Several techniques are introduced that allow integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. The experimental results obtained for large and complex industrial application-specific IC designs illustrate the feasibility of the proposed test scheme despite additional costs and efforts entailed in consolidating architectural changes and operations across a DFT flow.