High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET

• Published in: IEEE transactions on electron devices 2016-11, Vol.63 (11), p.4179-4184
• Main Authors: Hsieh, Dong-Ru, Lin, Jer-Yi, Kuo, Po-Yi, Chao, Tien-Sheng
• Format: Article
• Language: English
• Subjects: 3-D integrated circuits (ICs); Immune system; Integrated circuits; inversion mode (IM); Iron; junctionless (JL); Logic gates; Performance evaluation; Pi-gate (PG); poly-Si; Resistance; Silicon; Silicon nitride
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2016.2611021

In this paper, the Pi-gate (PG) poly-Si junction-less (JL) and inversion mode (IM) FETs with a high aspect ratio (A.R. = channel thickness/channel width ~ 3.4) have been successfully fabricated and demonstrated by a method without using the costly lithography technique. This method has some advantages: 1) the thickness of channels can be controlled simply by thickness of poly-Si layer; 2) the shape of channels can be controlled effectively by rectangular silicon nitride (Si 3 N 4 ) as hard masks; 3) the series resistance can be reduced by raised source/drain configurations; and 4) Si-compatible low thermal budget process. The PG polySi JL FETs show excellent electrical performance in terms of low gate overdrive voltage (VG-VTH = 2 V), extremely near ideal subthreshold swing (S.S.) ~68 mV/decade, steep average subthreshold swing (A.S.S.) ~ 73 mV/decade, smaller drain induced barrier lowering ~9 mV/V, a higher ON/OFF current ratio ~ 1.1 × 10 8 (VD = 1 V), and a better field-effect mobility (μFE) ~ 35 (cm 2 /Vs) as compared with PG poly-Si IM FETs. Thus, these devices are very promising for future 3-D integrated circuits applications.