An efficient two-level partitioning algorithm for VLSI circuits

• Main Authors: Jong-Sheng Cherng, Soo-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho
• Format: Conference Proceeding
• Language: English
• Subjects: Circuit synthesis; Clustering algorithms; Delay; Information science; Integrated circuit interconnections; Iterative algorithms; Partitioning algorithms; Process control; Size control; Very large scale integration
• DOI: 10.1109/ASPDAC.1999.759712

In this paper, a new two-level bipartitioning algorithm TLP, combining a hybrid clustering technique with an iterative improvement based partitioning process, is proposed. The hybrid clustering algorithm consisting of a local bottom-up clustering technique to merge modules and a global top-down ratio-cut technique for decomposition can be used to reduce the partitioning complexity and improve the performance. To generate a high-quality partitioning solution, a module migration based partitioning algorithm MMP is also proposed as the base partitioner for the TLP algorithm. The MMP algorithm implicitly promotes the move of clusters during the module migration processes by paying more attention to the neighbors of moved modules, relaxing the size constraints temporarily during the migration process, and controlling the module migration direction. Experimental results obtained show that the TLP algorithm generates stable and high-quality partitioning results. The TLP algorithm improves the unstable property of module migration based algorithms such as FM and STABLE in terms of the average net cut value. On the other hand, TLP outperforms MELO, GFM/sub t/ and CDIP/sub LA3/ by 23%, 7%, and 10%, respectively and is competitive with hMetis, ML/sub c/ and LSR/MFFS which have generated better results than many recent state-of-the-art partitioning algorithms.