A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic

This paper presents an Ultra-Low Leakage (ULL) 55nm Deeply Depleted Channel (DDC) process technology for low power Internet of Things (IoT) applications. The DDC ULL devices provide 67% reduction in threshold (V T ) variation due to Random Dopant Fluctuation (RDF). Circuit techniques such as subthre...

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Bibliographic Details
Main Authors: Patel, Harsh N., Roy, Abhishek, Yahya, Farah B., Liu, Ningxi, Calhoun, Benton, Kumeno, Kazuyuki, Yasuda, Makoto, Harada, Akihiko, Ema, Taiji
Format: Conference Proceeding
Language:English
Subjects:
body biasing
DDC
subthreshold and variation
ultra-low-leakage
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Summary:This paper presents an Ultra-Low Leakage (ULL) 55nm Deeply Depleted Channel (DDC) process technology for low power Internet of Things (IoT) applications. The DDC ULL devices provide 67% reduction in threshold (V T ) variation due to Random Dopant Fluctuation (RDF). Circuit techniques such as subthreshold operation and reverse body biasing (RBB) are co-designed with the technology to maximize the energy/power saving. A test chip implements a 1Kb 6T SRAM, an FIR filter, and a 51-stage RO to showcase how the technology works with circuit techniques to minimize energy. The 6T SRAM array operates reliably down to 200mV with a reduced leakage power of 7nW (85% lower compared to non-DDC devices). The FIR filter consumes just 4.5pJ/cycle operating at 0.36V at 200 KHz.
ISSN:2378-6558
DOI:10.1109/ESSDERC.2016.7599583