High speed PLL frequency synthesizer with synchronous frequency sweep

A technique for achieving high switching speed of the phase locked loop circuits is introduced and analyzed. This technique is based on using a pretuned signal that helps the PLL to reach the steady state condition in a relatively short time. This signal is temporally superimposed on the loop filter...

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Main Author: El-Ela, M.A.
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Communication switching
Filters
Frequency conversion
Frequency synthesizers
Phase locked loops
Stability
Steady-state
Voltage
Voltage-controlled oscillators
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description A technique for achieving high switching speed of the phase locked loop circuits is introduced and analyzed. This technique is based on using a pretuned signal that helps the PLL to reach the steady state condition in a relatively short time. This signal is temporally superimposed on the loop filter output to tune the voltage controlled oscillator of the loop. The system mathematical model was derived and proved effective in increasing the system stability and decreasing the settling time. Computer simulation and experimental results confirm the theoretical analysis.
doi_str_mv 10.1109/NRSC.1999.760886
format conference_proceeding
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ispartof Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249), 1999, p.C2/1-C2/9
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Circuits
Communication switching
Filters
Frequency conversion
Frequency synthesizers
Phase locked loops
Stability
Steady-state
Voltage
Voltage-controlled oscillators
title High speed PLL frequency synthesizer with synchronous frequency sweep
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