256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers

A 48 WL stacked 256-Gb V-NAND flash memory with a 3 b MLC technology is presented. Several vertical scale-down effects such as deteriorated WL loading and variations are discussed. To enhance performance, reverse read scheme and variable-pulse scheme are presented to cope with nonuniform WL characte...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2017-01, Vol.52 (1), p.210-217
Main Authors: Kang, Dongku, Jeong, Woopyo, Kim, Chulbum, Kim, Doo-Hyun, Cho, Yong Sung, Kang, Kyung-Tae, Ryu, Jinho, Kang, Kyung-Min, Lee, SungYeon, Kim, Wandong, Lee, Hanjun, Yu, Jaedoeg, Choi, Nayoung, Jang, Dong-Su, Lee, Cheon An, Min, Young-Sun, Kim, Moo-Sung, Park, An-Soo, Son, Jae-Ick, Kim, In-Mo, Kwak, Pansuk, Jung, Bong-Kil, Lee, Doo-Sub, Kim, Hyunggon, Ihm, Jeong-Don, Byeon, Dae-Seok, Lee, Jin-Yup, Park, Ki-Tae, Kyung, Kye-Hyun
Format: Article
Language:English
Subjects:
3-D NAND
3-D nonvolatile memory
48 WL stack 3-D
Calibration
Capacitance
Computer architecture
flash memory
Flash memory (computers)
IO design
Loading
NAND flash
Performance evaluation
Resistance
Temperature compensation
Timing
Vnand V-NAND
ZQ calibration
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Summary:A 48 WL stacked 256-Gb V-NAND flash memory with a 3 b MLC technology is presented. Several vertical scale-down effects such as deteriorated WL loading and variations are discussed. To enhance performance, reverse read scheme and variable-pulse scheme are presented to cope with nonuniform WL characteristics. For improved performance, dual state machine architecture is proposed to achieve optimal timing for BL and WL, respectively. Also, to maintain robust IO driver strength against PVT variations, an embedded ZQ calibration technique with temperature compensation is introduced. The chip, fabricated in a third generation of V-NAND technology, achieved a density of 2.6 Gb/mm 2 with 53.2 MB/s of program throughput.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2016.2604297