Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA

The Viterbi algorithm is commonly applied to a number of sensitive usage models including decoding convolutional codes used in communications such as satellite communication, cellular relay, and wireless local area networks. Moreover, the algorithm has been applied to automatic speech recognition an...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2017-01, Vol.64 (1), p.208-216
Main Authors: Mozaffari Kermani, Mehran, Singh, Vineeta, Azarderakhsh, Reza
Format: Article
Language:English
Subjects:
Adders
Algorithms
Application specific integrated circuits
Automatic speech recognition
Cellular communication
Circuit faults
Coding
Computer architecture
Computer simulation
Decoding
Embedded structures
Error correction & detection
Error detection
Fault detection
Field programmable gate arrays
Integrated circuits
Local area networks
look-ahead technique
Measurement
Performance degradation
recomputing with encoded operands
Reliability
Satellite communications
trellis
Viterbi algorithm
Viterbi algorithm detectors
Viterbi decoders
Wireless communications
Wireless networks
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Summary:The Viterbi algorithm is commonly applied to a number of sensitive usage models including decoding convolutional codes used in communications such as satellite communication, cellular relay, and wireless local area networks. Moreover, the algorithm has been applied to automatic speech recognition and storage devices. In this paper, efficient error detection schemes for architectures based on low-latency, low-complexity Viterbi decoders are presented. The merit of the proposed schemes is that reliability requirements, overhead tolerance, and performance degradation limits are embedded in the structures and can be adapted accordingly. We also present three variants of recomputing with encoded operands and its modifications to detect both transient and permanent faults, coupled with signature-based schemes. The instrumented decoder architecture has been subjected to extensive error detection assessments through simulations, and application-specific integrated circuit (ASIC) [32 nm library] and field-programmable gate array (FPGA) [Xilinx Virtex-6 family] implementations for benchmark. The proposed fine-grained approaches can be utilized based on reliability objectives and performance/implementation metrics degradation tolerance.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2016.2610187